module frq (
    input               clk,rstn,
    output      reg     clk_1k
);

reg [9:0]   count;
always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        clk_1k <= 1'b0;
        count <= 0;
    end else begin
        if (count == 499) begin
            count <= 0;
            clk_1k <= ~clk_1k;
        end else begin
            count <= count + 1;
        end
    end
end
endmodule //frq